Low hydrogen concentration charge-trapping layer structures for non-volatile memory
US8022465B2 · kind B2 · utility
2Cited by
16References
9Claims
0Family size
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Key dates
| Filing date | Nov 15, 2005 |
| Grant date | Sep 20, 2011 |
| Priority date | — |
| Expiry date | Nov 15, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
Abstract
Memory cells comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trapping structure comprises a bottom insulating layer, a first charge-trapping layer, and a second charge-trapping layer, wherein an interface between the bottom insulating layer and the substrate has a hydrogen concentration of less than about 3×1011/cm−2, and methods for forming such memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.