Reducing effects of program disturb in a memory device
US8023329B2 · kind B2 · utility
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55References
19Claims
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Key dates
| Filing date | Apr 20, 2010 |
| Grant date | Sep 20, 2011 |
| Priority date | — |
| Expiry date | Apr 20, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A selected word line that is coupled to cells for programming is biased with an initial programming voltage. The unselected word lines that are adjacent to the selected word line are biased at an initial Vpass. As the quantity of program/erase cycles on the memory device increases, the programming voltage required to successfully program the cells decreases incrementally. Vpass tracks the decrease of the programming voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.