Host memory interface for a parallel processor
US8024533B2 · kind B2 · utility
0Cited by
7References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2010 |
| Grant date | Sep 20, 2011 |
| Priority date | — |
| Expiry date | Sep 17, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4239
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory interface for a parallel processor which has an array of processing elements and can receive a memory address and supply the memory address to a memory connected to the processing elements. The processing elements transfer data to and from the memory at the memory address. The memory interface can connect to a host configured to access data in a conventional SDRAM memory device so that the host can access data in the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.