Stacked integrated circuits package system with passive components
US8026129B2 · kind B2 · utility
13Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2006 |
| Grant date | Sep 27, 2011 |
| Priority date | — |
| Expiry date | Jul 23, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked integrated circuit package system is provided forming a first stack layer having a first integrated circuit die on a first substrate, forming a second stack layer having a second integrated circuit die on a second substrate, and mechanically and electrically connecting a spacer layer having a first passive component between the second stack layer and the first stack layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.