Methods of forming low hydrogen concentration charge-trapping layer structures for non-volatile memory

US8026136B2 · kind B2 · utility

Assignee

• MACRONIX INTERNATIONAL CO., LTD. · TW

Inventors

• Yen-Hao Shih · Hsinchu, TW
• Min-Ta Wu · Zhejiang, CN
• Shih-Chin Lee · Hsinchu, TW
• Jung-Yu Hsieh · Saratoga Springs, US
• Erh-Kun Lai · Taichung, TW
• Kuang Yeu Hsieh · Hsinchu, TW

Key dates

• Filing date: Dec 26, 2007
• Grant date: Sep 27, 2011
• Expiry date: May 25, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/693

Abstract

Memory cells comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trapping structure comprises a bottom insulating layer, a first charge-trapping layer, and a second charge-trapping layer, wherein an interface between the bottom insulating layer and the substrate has a hydrogen concentration of less than about 3×1011/cm−2, and methods for forming such memory cells.