LDMOS with N-type isolation ring and method of fabricating the same
US8026549B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2008 |
| Grant date | Sep 27, 2011 |
| Priority date | — |
| Expiry date | Dec 19, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/519
Abstract
A semiconductor device and an IC chip are described. The deep N-well region is configured in a substrate. The P-well region surrounds a periphery of the deep N-well region. The gate structure is disposed on the substrate of the deep N-well region. The P-body region is configured in the deep N-well region at one side of the gate structure. The first N-type doped region is configured in the P-body region. The second N-type doped region is configured pin the deep N-well region at the other side of the gate structure. The first isolation structure is disposed between the gate structure and the second N-type doped region. The N-type isolation ring is configured in the deep N-well region and corresponding to an edge of the deep N-well region, wherein a doping concentration of the N-type isolation ring is higher than that of the deep N-well region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.