Semiconductor-device isolation structure
US8026571B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 2008 |
| Grant date | Sep 27, 2011 |
| Priority date | — |
| Expiry date | Jun 23, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturing method for a semiconductor-device isolation structure comprises providing a substrate with at least one shallow trench isolation structure, performing a salicide process that forms a recess on the surface of the shallow trench isolation structure, forming a cap film covering the substrate and filling the recess, performing an etching process to remove the cap film outside the recess, and forming a contact etch stop layer covering the substrate and filling the recess. Due to the filling recess with the cap film first, the contact etch stop layer covering the substrate and filling the recess does not have seams or voids.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.