Back-gated fully depleted SOI transistor
US8030145B2 · kind B2 · utility
20Cited by
12References
21Claims
0Family size
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Key dates
| Filing date | Jan 8, 2010 |
| Grant date | Oct 4, 2011 |
| Priority date | — |
| Expiry date | Mar 29, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/13091
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fully depleted semiconductor-on-insulator (FDSOI) transistor structure includes a back gate electrode having a limited thickness and aligned to a front gate electrode. The back gate electrode is formed in a first substrate by ion implantation of dopants through a first oxide cap layer. Global alignment markers are formed in the first substrate to enable alignment of the front gate electrode to the back gate electrode. The global alignment markers enable preparation of a virtually flat substrate on the first substrate so that the first substrate can be bonded to a second substrate in a reliable manner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.