Process for manufacturing a large-scale integration MOS device and corresponding MOS device
US8030192B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 22, 2006 |
| Grant date | Oct 4, 2011 |
| Priority date | — |
| Expiry date | Jul 28, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for manufacturing a MOS device and the MOS device manufactured thereby are disclosed. The process includes in a semiconductor layer forming a gate structure above the semiconductor layer; forming a first doped region within a first surface portion of the semiconductor layer; and irradiating the first doped region with electromagnetic radiation, to carry out annealing thereof. Prior to the irradiating step, a dielectric mirror is formed above a second surface portion of the semiconductor layer. The dielectric mirror, which may be of the Bragg-reflector type, reflects at least in part the electromagnetic radiation, and protects underlying regions from the electromagnetic radiation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.