Transistor formation using capping layer
US8030196B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jan 12, 2010 |
| Grant date | Oct 4, 2011 |
| Priority date | — |
| Expiry date | Jan 12, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A method of transistor formation using a capping layer in complimentary metal-oxide semiconductor (CMOS) structures is provided, the method including: depositing a conductive layer over an n-type field effect transistor (nFET) and over a p-type field effect transistor (pFET); depositing a capping layer directly over the conductive layer; etching the capping and conductive layers to form a capped gate conductor to gates of the nFET and pFET, respectively; ion-implanting the nFET transistor with a first dopant; and ion-implanting the pFET transistor with a second dopant, wherein ion-implanting a transistor substantially dopes its source and drain regions, but not its gate region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.