Low leakage ROM architecture

US8031542B2 · kind B2 · utility

Assignee

• SYNOPSYS, INC. · US

Inventors

• Vineet Kumar SACHAN · Ghaziabad, IN
• Deepak Sabharwal · Fremont, US
• Amit Khanuja · New Delhi, IN

Key dates

• Filing date: Sep 28, 2010
• Grant date: Oct 4, 2011
• Expiry date: Sep 28, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/711

Abstract

A Read only memory (ROM) with minimum leakage includes a ROM array including a first transistor, wherein a drain, a source, a gate, and a bulk of the first transistor is electrically connected to a logic zero in the idle state for ensuring zero junction and sub-threshold leakage current. The drain of the first transistor is electrically connected to a main bit line through a second transistor. The second transistor includes a gate, electrically connected to a first decoding circuit, a drain, electrically connected to the main bit line. A first reference bit line is electrically connected to a drain of a third transistor, wherein gate of the third transistor is electrically connected to a second decoding circuit for generating a stop read signal. A second reference bit line, electrically connected to the first decoding circuit through a first sensing unit for generating a stop pre-charge signal.