Patent · US Active

Method of forming dual damascene semiconductor device

US8034722B2 · kind B2 · utility

6Cited by
5References
13Claims
0Family size

Assignee

Inventors

Key dates

Filing dateApr 7, 2006
Grant dateOct 11, 2011
Priority date—
Expiry dateNov 19, 2026

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L21/76808
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A method of forming a dual damascene includes forming first, second and third material layers sequentially over a substrate. The first, second and third material layers have first, second and third thicknesses, respectively. An opening is etched within the first material layer while a portion or all of the thickness of the third layer is simultaneously removed. The ratio of the depth of the opening and the thickness of the third material layer removed, correspond to an etch selectivity of the first material layer and the second material layer. The etching operation may be automatically terminated to produce the opening with a predetermined depth.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.