Integrated circuitry
US8035129B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2010 |
| Grant date | Oct 11, 2011 |
| Priority date | — |
| Expiry date | Jun 22, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6728
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This invention includes methods of forming layers comprising epitaxial silicon, and field effect transistors. In one implementation, a method of forming a layer comprising epitaxial silicon comprises epitaxially growing a silicon-comprising layer from an exposed monocrystalline material. The epitaxially grown silicon comprises at least one of carbon, germanium, and oxygen present at a total concentration of no greater than 1 atomic percent. In one implementation, the layer comprises a silicon germanium alloy comprising at least 1 atomic percent germanium, and further comprises at least one of carbon and oxygen at a total concentration of no greater than 1 atomic percent. Other aspects and implementations are contemplated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.