Method and layout of semiconductor device with reduced parasitics

US8035140B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Albert Birner · Regensburg, DE
• Qiang Chen · Sollentuna, SE

Key dates

• Filing date: Jul 26, 2007
• Grant date: Oct 11, 2011
• Expiry date: Apr 17, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/664

Abstract

An semiconductor device is disclosed. The device includes a semiconductor body, a layer of insulating material disposed over the semiconductor body, and a region of gate electrode material disposed over the layer of insulating material. Also included are a source region adjacent to gate region and a drain region adjacent to the gate region. A gate connection is disposed over the semiconductor body, wherein the gate connection includes a region of gate electrode material electrically coupling a contact region to the gate electrode. An insulating region is disposed on the semiconductor body beneath the gate connection.