Bi-layer nFET embedded stressor element and integration to enhance drive current

US8035141B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Kevin K. Chan · Staten Island, US
• Abhishek Dube · Fishkill, US
• Jinghong Li · Poughquag, US
• Viorel Ontalus · Danbury, US
• Zhengmao Zhu · Poughkeepsie, US

Key dates

• Filing date: Oct 28, 2009
• Grant date: Oct 11, 2011
• Expiry date: Nov 4, 2029

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S257/903

Abstract

A semiconductor structure including a bi-layer nFET embedded stressor element is disclosed. The bi-layer nFET embedded stressor element can be integrated into any CMOS process flow. The bi-layer nFET embedded stressor element includes an implant damaged free first layer of a first epitaxy semiconductor material having a lattice constant that is different from a lattice constant of a semiconductor substrate and imparts a tensile strain in a device channel of an nFET gate stack. Typically, and when the semiconductor is composed of silicon, the first layer of the bi-layer nFET embedded stressor element is composed of Si:C. The bi-layer nFET embedded stressor element further includes a second layer of a second epitaxy semiconductor material that has a lower resistance to dopant diffusion than the first epitaxy semiconductor material. Typically, and when the semiconductor is composed of silicon, the second layer of the bi-layer nFET embedded stressor element is composed of silicon. Only the second layer of the bi-layer nFET embedded stressor element includes the implanted source/drain regions.