Neutralization of trapped charge in a charge accumulation layer of a semiconductor structure

US8035200B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• John M. Aitken · South Burlington, US
• Ethan H. Cannon · South Burlington, US
• Alvin W. Strong · South Burlington, US

Key dates

• Filing date: Jun 3, 2010
• Grant date: Oct 11, 2011
• Expiry date: Jun 3, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76275
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor structure. The semiconductor structure includes a semiconductor layer, a charge accumulation layer on top of the semiconductor layer, a doped region in direct physical contact with the semiconductor layer; and a device layer on and in direct physical contact with the charge accumulation layer. The charge accumulation layer includes trapped charges of a first sign. The doped region and the semiconductor layer forms a P−N junction diode. The P−N junction diode includes free charges of a second sign opposite to the first sign. The trapped charge in the charge accumulation layer exceeds a preset limit above which semiconductor structure is configured to malfunction. A first voltage is applied to the doped region. A second voltage is applied to the semiconductor layer. A third voltage is applied to the device layer. The third voltage exceeds the first voltage and the second voltage.