Stackable integrated circuit package system with recess
US8035207B2 · kind B2 · utility
20Cited by
22References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2006 |
| Grant date | Oct 11, 2011 |
| Priority date | — |
| Expiry date | Aug 27, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stackable integrated circuit package system is provided including forming an external interconnect having an interconnect non-recessed portion and an interconnect recessed portion, mounting an integrated circuit die over a paddle that is coplanar with the interconnect recessed portion, and forming an encapsulation having a recess over the external interconnect and the integrated circuit die with the external interconnect exposed at a side of the encapsulation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.