Dynamically adjustable erase and program levels for non-volatile memory
US8036044B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2009 |
| Grant date | Oct 11, 2011 |
| Priority date | — |
| Expiry date | Oct 5, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Degradation of non-volatile storage elements is reduced by adaptively adjusting erase-verify levels and program-verify levels. The number of erase pulses, or the highest erase pulse amplitude, needed to complete an erase operation is determined. When the number, or amplitude, reaches a limit, the erase-verify level is increased. As the erase-verify level is increased, the number of required erase pulses decreases since the erase operation can be completed more easily. An accelerating increase in the degradation is thus avoided. One or more program-verify levels can also be increased in concert with changes in the erase-verify level. The one or more program-verify levels can increase by the same increment as the erase-verify level to maintain a constant threshold voltage window between the erased state and a programmed state, or by a different increment. Implementations with binary or multi-level storage elements are provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.