Semiconductor memory device capable of suppressing a coupling effect of a test-disable transmission line
US8036053B2 · kind B2 · utility
1Cited by
2References
9Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 6, 2008 |
| Grant date | Oct 11, 2011 |
| Priority date | — |
| Expiry date | Aug 7, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1206
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Semiconductor device and semiconductor memory device include a plurality of internal circuits configured to perform test operations in response to their respective test mode signals and a plurality of test-mode control units configured to control the test operations of the internal circuits to be disabled in response to a test-off signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.