Method and system for reducing overlay errors in semiconductor volume production using a mixed tool scenario

US8039181B2 · kind B2 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Rolf Seltmann · Dresden, DE
• Jens Busch · Radebeul, DE
• Uwe Schulze · Dresden, DE

Key dates

• Filing date: Jun 2, 2009
• Grant date: Oct 18, 2011
• Expiry date: Mar 24, 2030

Classification

• Technology area (CPC G): Physics
• CPC primary: G03F9/7088
• WIPO field: Optics
• WIPO sector: Instruments

Abstract

By taking into consideration the combination of the substrate holders in various lithography tools used during the imaging to two subsequent device layers, enhanced alignment accuracy may be accomplished. Furthermore, restrictive tool dedications for critical lithography processes may be significantly relaxed by providing specific overlay correction data for each possible process flow, wherein, in some illustrative embodiments, a restriction of the number of possible process flows may be accomplished by implementing a rule for selecting a predefined substrate holder when starting the processing of an associated group of substrates.