Method and apparatus for improving transactional memory commit latency
US8041900B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2008 |
| Grant date | Oct 18, 2011 |
| Priority date | — |
| Expiry date | Aug 30, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention provide a system that executes transactions on a processor that supports transactional memory. The system starts by executing the transaction on the processor. During execution of the transactions, the system places stores in a store buffer. In addition, the system sets a stores_encountered indicator when a first store is placed in the store buffer during the transaction. Upon completing the transaction, the system determines if the stores_encountered indicator is set. If so, the system signals a cache to commit the stores placed in the store buffer during the transaction to the cache and then resumes execution of program code following the transaction when the stores have been committed. Otherwise, the system resumes execution of program code following the transaction without signaling the cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.