Method for compaction of timing exception paths
US8042085B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2008 |
| Grant date | Oct 18, 2011 |
| Priority date | — |
| Expiry date | Aug 26, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique and apparatus for reducing the complexity of optimizing the performance of a designed semiconductor circuit is disclosed. This technique of path compaction is used to reduce the time taken for optimization. The path compaction tool is used in design optimization to reduce the optimizer execution time. Compaction helps readability, usability and reduces synthesis and static timing analyzer (STA) runtime. The aim of path compaction is to reduce the number of constraints the optimizer has to go through during the optimization process. Path compaction has three dimensions. The first is to reduce number of “-through” elements in the constraint, thereby reducing the complexity of constraints developed The second is to combine the paths to reduce the number of constraints. The third is to combine the constraints to reduce the number of constraints to be checked and optimized. Path compaction is used when generating timing exception using timing exception tools.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.