Patent · US Expired

Semiconductor wafer with electrically connected contact and test areas

US8044394B2 · kind B2 · utility

1Cited by

16References

20Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Werner Ertle · Neubiberg, DE
Bernd Goller · Otterfing, DE
Michael Horn · South Setauket, US
Bernd Kothe · Fontainebleau, FR

Key dates

Filing date	Jul 29, 2003
Grant date	Oct 25, 2011
Priority date	—
Expiry date	Aug 22, 2025

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/14
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

The invention relates to an arrangement of contact areas and test areas on patterned semiconductor chips. The contact areas and the test areas are electrically connected to one another via a conduction web. Whereas the contact areas are arranged in a first region, which has no components of an integrated circuit, the test areas lie in a second region of the top side of the semiconductor chip, which region has components of an integrated circuit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.