Memory device with a length-controllable channel
US8044449B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2008 |
| Grant date | Oct 25, 2011 |
| Priority date | — |
| Expiry date | Feb 16, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/395
Abstract
A memory device is provided. The memory device includes a substrate, a trench having an upper portion and a lower portion formed in the substrate, a trench capacitor formed in the lower portion of the trench, a collar dielectric layer formed on a sidewall of the trench capacitor and extending away from a top surface of the substrate, a first doping region formed on a side of the upper portion of the trench in the substrate for serving as source/drain, a conductive layer formed in the trench and electrically connected to the first doping region, a top dielectric layer formed on conductive layer, a gate formed on the top dielectric layer, an epitaxy layer formed on both sides of the gate and on the substrate and a second doping area formed on a top of the epitaxy layer for serving as source/drain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.