Methods of fabricating transistors including dielectrically-supported gate electrodes and related devices

US8049252B2 · kind B2 · utility

Assignee

• Cree, Inc. · US

Inventors

• Richard Peter Smith · Carrboro, US
• Scott Sheppard · Chapel Hill, US

Key dates

• Filing date: Mar 16, 2010
• Grant date: Nov 1, 2011
• Expiry date: Mar 16, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/8503

Abstract

Transistors are fabricated by forming a protective layer having a first opening extending therethrough on a substrate, forming a dielectric layer on the protective layer having a second opening extending therethrough that is wider than the first opening, and forming a gate electrode in the first and second openings. A first portion of the gate electrode laterally extends on surface portions of the protective layer outside the first opening, and a second portion of the gate electrode is spaced apart from the protective layer and laterally extends beyond the first portion on portions of the dielectric layer outside the second opening. Related devices and fabrication methods are also discussed.