Substrate-level assembly for an integrated device, manufacturing process thereof and related integrated device
US8049287B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2008 |
| Grant date | Nov 1, 2011 |
| Priority date | — |
| Expiry date | Oct 7, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04R19/005
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A substrate-level assembly having a device substrate of semiconductor material with a top face and housing a first integrated device, including a buried cavity formed within the device substrate, and with a membrane suspended over the buried cavity in the proximity of the top face. A capping substrate is coupled to the device substrate above the top face so as to cover the first integrated device in such a manner that a first empty space is provided above the membrane. Electrical-contact elements electrically connect the integrated device with the outside of the substrate-level assembly. In one embodiment, the device substrate integrates at least a further integrated device provided with a respective membrane, and a further empty space, fluidly isolated from the first empty space, is provided over the respective membrane of the further integrated device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.