System and method for circuit symbolic timing analysis of circuit designs
US8050904B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2006 |
| Grant date | Nov 1, 2011 |
| Priority date | — |
| Expiry date | Mar 3, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, data processing system, and computer program product are provided for performing time-based symbolic simulation. A delay-aware representation of a circuit is created that includes a plurality of circuit nodes. The data-aware representation is simulated. In particular, the simulator simulates transitions from a first set of circuit nodes to a second set of circuit nodes selected from the plurality of circuit nodes, the simulating based on executing a first set of simulation events. A second set of simulation events is then generated in response to executing the first set of simulation events. During the simulation, a time is computed for each of the transitions. An an event scheduling diagram is constructed during simulation. The event scheduling diagram depicts the transitions and the times of the transitions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.