Method of forming a wafer level package
US8053281B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2008 |
| Grant date | Nov 8, 2011 |
| Priority date | — |
| Expiry date | Dec 2, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for forming a microelectronic package at a wafer level. Such method can include providing a semiconductor wafer having a surface with a pattern of electrical contacts thereon. An interposer component can be provided which has a compliant dielectric layer bonded to a conductive layer. A pattern of holes can be formed through the compliant dielectric layer and the conductive layer which corresponds to the pattern of electrical contacts. The compliant dielectric layer can be contacted with the semiconductor wafer surface so that the pattern of holes is in an aligned position with the pattern of contacts and the compliant dielectric layer and the semiconductor wafer surface then bonded in the aligned position to unite the semiconductor wafer and the interposer component to form a wafer level semiconductor package. The wafer level semiconductor package can be diced to form individual semiconductor chip packages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.