BGA package with traces for plating pads under the chip
US8053349B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2008 |
| Grant date | Nov 8, 2011 |
| Priority date | — |
| Expiry date | Jun 27, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/00014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor flip-chip ball grid array package (600) with one-metal-layered substrate. The sites (611) of a two-dimensional array become usable for attaching solder balls of the signal (non-common net assignment) I/O type to the substrate under the chip area (601), when the sites can be routed for metal plating (620). The space to place a maximum number (614) of signal routing traces is opened up by interrupting the periodicity of the site array from the edge (602) of the substrate towards the center under the chip. The periodicity is preferably interrupted by depopulating entire aligned lines and rows of the two-dimensional array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.