Reduced wafer warpage in semiconductors by stress engineering in the metallization system

US8053354B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Matthias Lehr · Dresden, DE
• Frank Koschinsky · Radebeul, DE
• Joerg Hohage · Dresden, DE

Key dates

• Filing date: Sep 17, 2009
• Grant date: Nov 8, 2011
• Expiry date: Nov 24, 2029

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02P80/30
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In complex metallization systems of sophisticated semiconductor devices, appropriate stress compensation mechanisms may be implemented in order to reduce undue substrate deformation during the overall manufacturing process. For example, additional dielectric material and/or functional layers of one or more metallization layers may be provided with appropriate internal stress levels so as to maintain substrate warpage at a non-critical level, thereby substantially reducing yield losses in the manufacturing process caused by non-reliable attachment of substrates to substrate holders in process and transport tools.