Stacked, interconnected semiconductor package
US8053880B2 · kind B2 · utility
3Cited by
16References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2009 |
| Grant date | Nov 8, 2011 |
| Priority date | — |
| Expiry date | Oct 14, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1815
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic component is disclosed including a plurality of stacked semiconductor packages. A first such embodiment includes an internal connector for electrically coupling the stacked semiconductor packages. A second such embodiment includes an external connector for electrically coupling the stacked semiconductor packages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.