Memory control device and methods thereof
US8055939B2 · kind B2 · utility
1Cited by
8References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2008 |
| Grant date | Nov 8, 2011 |
| Priority date | — |
| Expiry date | Oct 16, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2043
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes establishing a first link between a first processor device and a first memory module at a first time. A second link is established between a second processor device and a second memory module at a second time. In response to receiving a first event indicator, a third link is established between the first processor device and the second memory module at a third time, the third time after the first time and the second time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.