Semiconductor die structures for wafer-level chipscale packaging of power devices, packages and systems for using the same, and methods of making the same
US8058732B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2008 |
| Grant date | Nov 15, 2011 |
| Priority date | — |
| Expiry date | Dec 5, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed are semiconductor die structures that enable a die having a vertical power device to be packaged in a wafer-level chip scale package where the current-conducting terminals are present at one surface of the die, and where the device has very low on-state resistance. In an exemplary embodiment, a trench and an aperture are formed in a backside of a die, with the aperture contacting a conductive region at the top surface of the die. A conductive layer and/or a conductive body may be disposed on the trench and aperture to electrically couple the backside current-conducting electrode of the device to the conductive region. Also disclosed are packages and systems using a die with a die structure according to the invention, and methods of making dice with a die structure according to the invention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.