Evaluation circuit and method for detecting and/or locating faulty data words in a data stream Tn
US8060800B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2004 |
| Grant date | Nov 15, 2011 |
| Priority date | — |
| Expiry date | May 28, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31703
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An evaluation circuit and method for detecting faulty data words in a data stream is disclosed. In one embodiment the evaluation circuit according to the invention includes a first linear automaton circuit and also a second linear automaton circuit connected in parallel, each having a set of states z, which have a common input line for receiving a data stream Tn. The first linear automaton circuit and the second linear automaton circuit are designed such that a first signature and a second signature, respectively, can be calculated. Situated downstream of the two linear automaton circuits are respectively a first logic combination gate and a second logic combination gate, which compare the signature respectively calculated by the linear automaton circuit with a predeterminable good signature and output a comparison value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.