Compact semiconductor package with integrated bypass capacitor and method
US8062932B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2008 |
| Grant date | Nov 22, 2011 |
| Priority date | — |
| Expiry date | Jan 16, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A top-side cooled compact semiconductor package with integrated bypass capacitor is disclosed. The top-side cooled compact semiconductor package includes a circuit substrate with terminal leads, numerous semiconductor dies bonded atop the circuit substrate, numerous elevation-adaptive interconnection plates for bonding and interconnecting top contact areas of the semiconductor dies with the circuit substrate, a first member of the elevation-adaptive interconnection plates has a first flat-top area and a second member of the elevation-adaptive interconnection plates has a second flat-top area in level with the first flat-top area, a bypass capacitor, having two capacitor terminals located at its ends, stacked atop the two interconnection plate members while being bonded thereto via the first flat-top area and the second flat-top area for a reduced interconnection parasitic impedance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.