Method to increase effective MOSFET width
US8062951B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2007 |
| Grant date | Nov 22, 2011 |
| Priority date | — |
| Expiry date | Jul 26, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0278
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An epitaxial layer of silicon (Si) or silicon-germanium (SiGe) extends over the edge of silicon trench isolation (STI), thereby increasing the effective width of an active silicon region (RX) bordered by the STI. The RX region may have a <100> crystal orientation. An effective width of an FET device formed in the RX region may be increased, therefore performance may be improved with same density. Isolation may not be degraded since RX-to-RX distance is same at bottom. Junction capacitance may be reduced since part of the RX is on STI.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.