Microelectronic package containing silicon patches for high density interconnects, and method of manufacturing same
US8064224B2 · kind B2 · utility
141Cited by
10References
20Claims
0Family size
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Key dates
| Filing date | Mar 31, 2008 |
| Grant date | Nov 22, 2011 |
| Priority date | — |
| Expiry date | May 12, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10674
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A microelectronic package comprises a substrate (110), a silicon patch (120) embedded in the substrate, a first interconnect structure (131) at a first location of the silicon patch and a second interconnect structure (132) at a second location of the silicon patch, and an electrically conductive line (150) in the silicon patch connecting the first interconnect structure and the second interconnect structure to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.