Method for message processing on a programmable logic device
US8065130B1 · kind B1 · utility
5Cited by
29References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 13, 2009 |
| Grant date | Nov 22, 2011 |
| Priority date | — |
| Expiry date | Feb 11, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L45/60
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, configurable logic of an integrated circuit is configured to have a plurality of thread circuits and a memory. Messages are received to the integrated circuit for storage in the memory. The memory is accessed with the plurality of threads to concurrently process a plurality of the messages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.