Multi-layer circuit assembly and process for preparing the same
US8065795B2 · kind B2 · utility
0Cited by
25References
7Claims
0Family size
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Key dates
| Filing date | Jun 8, 2007 |
| Grant date | Nov 29, 2011 |
| Priority date | — |
| Expiry date | Sep 28, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49158
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Processes for fabricating a multi-layer circuit assembly and a multi-layer circuit assembly fabricated by such processes are provided. The process includes (a) providing a substrate at least one area of which comprises a plurality of vias, these area(s) having a via density of 500 to 10,000 holes/square inch (75 to 1550 holes/square centimeter); (b) applying a dielectric coating onto all exposed surfaces of the substrate to form a conformal coating thereon; and (c) applying a layer of metal to all surfaces of the substrate. Additional processing steps such as circuitization may be included.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.