Integrated circuit package system for package stacking and manufacturing method thereof
US8067272B2 · kind B2 · utility
0Cited by
25References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2009 |
| Grant date | Nov 29, 2011 |
| Priority date | — |
| Expiry date | Oct 20, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stackable multi-chip package system is provided including forming an external interconnect having a base and a tip, connecting a first integrated circuit die and the base, stacking a second integrated circuit die over the first integrated circuit die in an active side to active side configuration, connecting the second integrated circuit die and the base, and molding the first integrated circuit die, the second integrated circuit die, and the external interconnect partially exposed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.