Application of different isolation schemes for logic and embedded memory
US8067279B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2009 |
| Grant date | Nov 29, 2011 |
| Priority date | — |
| Expiry date | Jun 22, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.