Chip scale package having flip chip interconnect on die paddle
US8067823B2 · kind B2 · utility
6Cited by
15References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 15, 2005 |
| Grant date | Nov 29, 2011 |
| Priority date | — |
| Expiry date | Oct 9, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A flip chip lead frame package includes a die and a lead frame having a die paddle and leads, and has interconnection between the active site of the die and the die paddle. Also, methods for making the package are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.