Embedded integrated circuit package system and method of manufacture thereof
US8067832B2 · kind B2 · utility
0Cited by
11References
17Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 9, 2010 |
| Grant date | Nov 29, 2011 |
| Priority date | — |
| Expiry date | Dec 9, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/4602
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacture of an embedded integrated circuit package system includes: forming a first conductive pattern on a first structure; connecting a first integrated circuit die, having bumps on a first active side, directly on the first conductive pattern by the bumps; forming a substrate forming encapsulation to cover the first integrated circuit die and the first conductive pattern; forming a channel in the substrate forming encapsulation; and applying a conductive material in the channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.