Compound logic flip-flop having a plurality of input stages
US8072252B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 11, 2008 |
| Grant date | Dec 6, 2011 |
| Priority date | — |
| Expiry date | Jul 28, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/096
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A compound logic flip-flop. The flip-flop includes a plurality of input stages, wherein each of the input stages is coupled to receive at least one input signal and a clock signal. Each of the plurality of input (i.e. ‘master’) stages is configured to perform a corresponding input logic function during a first phase of a clock cycle and to store a result of the corresponding input logic function. The flip-flop further includes an output (i.e. ‘slave’) stage coupled to receive the clock signal and the results of the input logic functions from each of the plurality of input stages. The output stage is configured, during a second phase of the clock cycle, to logically combine the results of the input logic functions by performing an output logic function and provide an output signal based on a result of the output logic function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.