Method and apparatus for detecting clock gating opportunities in a pipelined electronic circuit design
US8073669B2 · kind B2 · utility
5Cited by
16References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2007 |
| Grant date | Dec 6, 2011 |
| Priority date | — |
| Expiry date | Dec 24, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pipeline electronic circuit and design methodology enables power conservation in the stages of the pipeline via a simulation that identifies clock-gating opportunities among the stages of the pipeline. In one embodiment, simulation results assist a designer in the design of the pipeline electronic circuit to achieve power conservation by incorporating clock-gating circuitry among the stages of the pipeline at clock gating opportunity locations that the simulation identifies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.