Providing extended precision in SIMD vector arithmetic operations
US8074058B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2009 |
| Grant date | Dec 6, 2011 |
| Priority date | — |
| Expiry date | Oct 22, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into first and second vector registers, respectively. Each data element comprises N bits. Next, an arithmetic instruction is fetched from memory. The arithmetic instruction is decoded. Then, the first vector register and the second vector register are read from the register file. The present invention executes the arithmetic instruction on corresponding data elements in the first and second vector registers. The resulting element of the execution is then written into the accumulator. Then, the resulting element is transformed into an N-bit width element and written into a third register for further operation or storage in memory. The transformation of the resulting element can include, for example, rounding, clamping, and/or shifting the element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.