Memory and method for sensing data in a memory using complementary sensing scheme
US8077533B2 · kind B2 · utility
4Cited by
12References
20Claims
0Family size
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Key dates
| Filing date | Jan 23, 2006 |
| Grant date | Dec 13, 2011 |
| Priority date | — |
| Expiry date | Sep 20, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a memory (100), a local data line pair (116, 118) is precharged to a first logic state and a global data line pair (101, 104) is precharged to a second logic state. A selected memory cell is coupled to the local data line pair (116, 118) to develop a differential local data line voltage. The differential local data line voltage is subsequently amplified to form an amplified differential local data line voltage. A selected one of the global data line pair (101, 104) is driven to the first logic state in response to the amplified differential local data line voltage to form a differential global data line voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.