Self aligned contact in a semiconductor device and method of fabricating the same
US8080459B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 15, 2004 |
| Grant date | Dec 20, 2011 |
| Priority date | — |
| Expiry date | Aug 23, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/511
Abstract
A method of fabricating a self-aligned contact in a semiconductor device, in accordance with one embodiment of the present invention, includes etching a trench in a core area and partially extending into a termination area of a substrate. A first oxide is grown on the substrate proximate the trench. A polysilicon layer is deposited in the core area and the termination area. The polysilicon layer is selectively etched to form a gate region in the core area portion of the trench. The etching of the polysilicon layer also forms a first portion of a gate interconnect region in the termination area portion of the trench and a second portion in the termination area outside of the trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.