Patent · US Active

Methods for processing silicon on insulator wafers

US8080464B2 · kind B2 · utility

0Cited by

2References

18Claims

0Family size

Assignee

MEMC Electronic Materials, Inc. · US

Inventors

Swapnil Dhumal · Bengaluru, IN
Lawrence P. Flannery · Warrenton, US
Thomas A. Torack · Oakland, US
John A. Pitney · Saint Peters, US

Key dates

Filing date	Dec 17, 2010
Grant date	Dec 20, 2011
Priority date	—
Expiry date	Dec 17, 2030

Classification

Technology area (CPC H)Electricity
CPC primaryH01L21/7624
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Methods are provided for etching and/or depositing an epitaxial layer on a silicon-on-insulator structure comprising a handle wafer, a silicon layer, and a dielectric layer between the handle wafer and the silicon layer. The silicon layer has a cleaved surface defining an outer surface of the structure. The cleaved surface of wafer is then etched while controlling a temperature of the reactor such that the etching reaction is kinetically limited. An epitaxial layer is then deposited on the wafer while controlling the temperature of the reactor such that a rate of deposition on the cleaved surface is kinetically limited.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.