Method of implementing a capacitor in an integrated circuit
US8084297B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 5, 2010 |
| Grant date | Dec 27, 2011 |
| Priority date | — |
| Expiry date | Aug 5, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of implementing a capacitor in an integrated circuit package is disclosed. The method comprises coupling the capacitor to a first surface of a substrate of the integrated circuit package; positioning an integrated circuit die over the capacitor, wherein the integrated circuit die has a first plurality of solder bumps and a second plurality of solder bumps separated by a region having no solder bumps; coupling the integrated circuit die to the first surface of the substrate over the capacitor, wherein the region having no solder bumps is positioned over the capacitor; and encapsulating the integrated circuit die and the capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.